Using Multiple Clocks in Highlevel Synthesis to overcome unbalanced clock cycles

Keyphrases

• Latency 100%
• Execution Time 100%
• High-level Synthesis 100%
• Multiple Clocks 100%
• Longest Path 50%
• Straight Line 50%
• Common Divisor 50%
• Line Codes 50%
• L1-L2 25%
• Scheduler 25%
• Vitis 25%
• Verilog 25%
• Control Flow Graph 25%
• Nested Loops 25%
• Conditional Statement 25%
• Hardware Circuit 25%
• LLVM Compiler 25%
• C + + 25%
• Common Clock 25%
• CLK1 25%
• Global Scheduling 25%
• Clock Period 25%
• High-level Synthesis Tools 25%

Computer Science

• Execution Time 100%
• Clock Cycle 100%
• High Level Synthesis 75%
• Longest Path 50%
• Verilog 25%
• Control-Flow Graph 25%
• Nested Loop 25%
• Conditional Statement 25%
• Synthesis Tool 25%
• Clock Period 25%
• Computer Hardware 25%