Abstract
High-level Synthesis (HLS) is a technique to compile C/C++ algorithmic code directly to hardware circuits (Verilog/VHDL). Typically, HLS schedulers partition the graph of operations to layers L1,L2, ⋯, Lk where the operations in each layer are executed in consecutive clock cycles. The execution time for each layer could be different, leading to unbalanced cycles because cannot ensure finding optimal clock-width by finding a common divisor between the layer's execution time. Previous works like Re-clocking and Chaining attempt to balance the scheduling layers by moving operations from proceeding layers to the current one, optimizing clock latency, and finding optimal clock-width. However, unlike to solution proposed here, these techniques may sometimes fail to obtain the optimal solution because they cannot ensure finding a common divisor between the layer's execution time. The proposed technique is to use separate overlapping clocks clk1,clk2, ⋯, clkk for each layer wherein the 0 → 1 transion in each clki occures at Σ latency({Lj) | Lj} ∈ (longest path to Li). and 1 → 0 transition in each clki occurs at (Σ latency({Lj) | Lj} ∈ (longest path to Li) + Lilatency In this way, the time-waists of unbalanced latencies disappear into an optimal common clock period of each clki for straight line code, and statistically near the optimal for non-straight line code. A second contribution of this work is an extension of this technique to perform global scheduling, i.e., obtain balanced layers for multiple basic blocks of a full control-flow graph (e.g., a combination of nested-loops and conditional statements). This technique was implemented in the LLVM compiler. Results suggest significant improvements in execution time and power compared to a commercial HLS tool (Vitis).
Original language | English |
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Title of host publication | Proceedings - 2023 16th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2023 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 552-559 |
Number of pages | 8 |
ISBN (Electronic) | 9798350393613 |
DOIs | |
State | Published - 2023 |
Event | 16th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2023 - Singapore, Singapore Duration: 18 Dec 2023 → 21 Dec 2023 |
Publication series
Name | Proceedings - 2023 16th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2023 |
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Conference
Conference | 16th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2023 |
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Country/Territory | Singapore |
City | Singapore |
Period | 18/12/23 → 21/12/23 |
Bibliographical note
Publisher Copyright:© 2023 IEEE.
ASJC Scopus subject areas
- Artificial Intelligence
- Computer Networks and Communications
- Computer Science Applications
- Hardware and Architecture