Unifying wire and time scheduling for highlevel synthesis

Keyphrases

• High-level Synthesis 100%
• Time Scheduling 100%
• Tree Structure 50%
• Induced Subgraph 50%
• Compiler 50%
• Memory Operations 50%
• Verilog 50%
• LLVM Compiler 50%
• Semi-global 50%
• Wirelength 50%
• Logic Operation 50%
• VLSI chip 50%

Computer Science

• Verilog 100%
• Memory Operation 100%
• Application Specific Integrated Circuit 100%
• Optimal Product 100%
• Logical Operation 100%

Mathematics

• Minimizes 100%
• Tree-Like 50%
• Induced Subgraph 50%
• Formal Model 50%