Wire scaling is becoming problematic for semi-global and global wires in sub 40nm ASIC/VLSI chips. We propose an algorithm that simultaneously minimizes the time T and wire-lengths W for highlevel synthesis from C to Verilog. The program is compiled to a graphs G of arithmetic/logical and memory operations. We developed a formal model wherein the optimal product W × T of a given G can be resolved. The proposed algorithm for general Gs works by recursively decomposing G to either grid-like or tree-like induced sub-graphs and combines their optimal solutions. We have implemented this algorithm in the LLVM compiler and obtained an HLS compiler that successfully minimizes both W × T of the resulting circuits.
|Title of host publication||Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||8|
|State||Published - 16 Nov 2018|
|Event||12th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018 - Hanoi, Viet Nam|
Duration: 12 Sep 2018 → 14 Sep 2018
|Name||Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018|
|Conference||12th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018|
|Period||12/09/18 → 14/09/18|
Bibliographical notePublisher Copyright:
© 2018 IEEE.
- Highlevel synthesis
ASJC Scopus subject areas
- Hardware and Architecture
- Control and Systems Engineering