## Abstract

A new theoretical model for reconfigurable processor arrays is introduced. Most of the models considered in the literature are similar to the reconfigurable mesh (RMESH), in which each processing element (PE) is connected to its four neighbors by reconfigurable buses. In the new model, called the "well-connected processor array" (wecpar), every PE is connected to each neighbor by k ≥ 1 point-to-point lines, and it also controls the switching between those lines. k is called the connectivity of the wecpar. Any line entering the PE can either be connected to the PE itself, or it can be connected by the PE to another line, thus enabling complex switching configurations. This model is suitable for arrays in which the computation and memory areas of a PE are very much larger than a switch area. The concept of a burden placed on a PE by the lines connected to or passing through it is introduced. This is used to derive a lower bound of k = Ω(d ^{3}/^{2}/e) on the connectivity required by a wecpar to embed any graph of degree ≥d with expansion e; for e = 1, this result is sharp. Various other issues are examined: graph embeddings, algorithms, broadcasting, routing, and self-simulation. A novel transportation-type routing method utilizes the connectivity for efficient routing. A sample algorithmic result is that an n-point FFT can be done in logarithmic time on a wecpar of n PEs with a connectivity of √n/2.

Original language | English |
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Article number | 6361379 |

Pages (from-to) | 1287-1295 |

Number of pages | 9 |

Journal | IEEE Transactions on Computers |

Volume | 63 |

Issue number | 5 |

DOIs | |

State | Published - May 2014 |

## Keywords

- Graph embeddings
- multi-connected processing elements
- parallel computing
- point-to-point communications
- reconfigurable processor array
- routing
- self-simulation
- wecpar

## ASJC Scopus subject areas

- Software
- Theoretical Computer Science
- Hardware and Architecture
- Computational Theory and Mathematics