Synthesis for variable pipelined function units

Yosi Ben-Asher, Nadav Rotem

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


Usually, in high level hardware synthesis, all functional units of the same type have a fixed known "length" (number of stages) and the scheduler mainly determines when each unit is activated. We focus on scheduling techniques for the high-level synthesis of pipelined functional units where the number of stages of these operations is a free parameter of the synthesis. This problem is motivated by the ability to create pipelined functional units, such as multipliers, with different pipe lengths. These units have different characteristics in terms of parallelism level, frequency, latency, etc. In this paper presents the variable pipeline scheduler (VPS). The ability to synthesize variable pipelined units expands the known scheduling problem of high-level synthesis to include a 2D search for a minimal number of instances and their desired number of stages. The proposed search procedure is based on algorithms that find a local minima in a d-dimensional grid, thus avoiding the need to evaluate all possible points in the space. We have implemented a C language compiler for VPS. Our results demonstrate that using variable pipeline units can reduce the overall resource usage and improve the execution time.

Original languageEnglish
Title of host publication2008 International Symposium on System-on-Chip Proceedings, SOC 2008
StatePublished - 2008
Event2008 International Symposium on System-on-Chip, SOC 2008 - Tampere, Finland
Duration: 5 Nov 20086 Nov 2008

Publication series

Name2008 International Symposium on System-on-Chip Proceedings, SOC 2008


Conference2008 International Symposium on System-on-Chip, SOC 2008

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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