Abstract
One possible solution to the verification crisis is to bridge the gap between formal verification and simulation by using hybrid techniques. This paper presents a study of such a functional verification methodology that uses coverage of formal models to specify tests. This was applied to a modern superscalar microprocessor and the resulting tests were compared to tests generated using existing methods. The results showed some 50% improvement in transition coverage with less than a third the number of test instructions, demonstrating that hybrid techniques can significantly improve functional verification.
| Original language | English |
|---|---|
| Pages (from-to) | 970-975 |
| Number of pages | 6 |
| Journal | Proceedings - Design Automation Conference |
| State | Published - 1999 |
| Externally published | Yes |
| Event | Proceedings of the 1999 36th Annual Design Automation Conference (DAC) - New Orleans, LA, USA Duration: 21 Jun 1999 → 25 Jun 1999 |
ASJC Scopus subject areas
- Hardware and Architecture
- Control and Systems Engineering