Counter mode is one of the standard modes of operation for block ciphers. It has performance advantages due to its high parallelism. For a given key and a 96-bit IV, a 128-bit ciphertext block is computed by XOR-ing the corresponding plaintext block with the encryption of a unique 128-bit Counter Block. The Counter Block values are generated by incrementing a 32-bit counter that is concatenated to the 96-bit IV. In this paper, we show how to leverage the fact that the only 32 bits of the Counter Block are incremented, to gain a noticeable improvement in software implementations, and savings in hardware implementations for AES-CTR mode. We show a new optimization that speeds up a table-based software implementation by a factor of 1.11x on the 2nd Generation Intel Core Processor, and by 1.08x when using the AES-NI. This optimization speeds up the CTR mode by a factor of 1.18x on the 4th Generation Intel Core Processor.