RESTRUCTURING HEXAGONAL ARRAYS OF PROCESSORS IN THE PRESENCE OF FAULTS.

The issue of fault-tolerance in VLSI processing arrays has been the subject of several recent studies where different schemes for achieving fault-tolerance have been proposed. We concentrate here on fault-tolerance in hexagonal arrays, while most previous publications dealt with fault-tolerance in linear and rectangular arrays. Hexagonal arrays have been used for various computational algorithms and were shown to be more flexible when reconfiguring the array to match a given algorithm. It is, therefore, appropriate to develop a fault-tolerance strategy suitable for these processing arrays.