Reducing memory constraints in modulo scheduling synthesis for FPGAs

Keyphrases

• Memory Constraints 100%
• Modulo Scheduling 100%
• Execution Time 40%
• High-level Synthesis 40%
• Resource Constraints 30%
• Parallelization 20%
• Scheduling Techniques 20%
• Parallel Memory 20%
• Delay Constraint 20%
• Memory Reference 20%
• Synthesis Methods 10%
• Parallelizing 10%
• Repeated Application 10%
• Current Solution 10%
• Time Application 10%
• Opposite Problem 10%
• For Loop 10%
• Loop Acceleration 10%
• Successive Iteration 10%
• Synthesis Time 10%
• Shift Operation 10%
• Software Execution 10%
• Dummy Operations 10%

Computer Science

• Modulo Scheduling 100%
• Field Programmable Gate Arrays 100%
• Execution Time 40%
• High Level Synthesis 40%
• Resource Constraint 30%
• Memory Reference 20%
• Parallelism 20%
• Delay Constraint 20%
• Interactivity 20%
• Experimental Result 10%
• Repeated Application 10%
• Maximal Number 10%
• Synthesis Technique 10%
• Time Application 10%
• Shift Operation 10%