As the demand for higher data rates increases, commercial analog-to-digital converters (ADCs) are more commonly being implemented with multiple on-chip converters whose outputs are time-interleaved. The distortion generated by time-interleaved ADCs is now not only a function of the nonlinear behavior of the constituent circuitry, but also mismatches associated with interleaving multiple output streams. To mitigate distortion generated by time-interleaved ADCs, we have developed a polyphase NonLinear EQualizer (pNLEQ) which is capable of simultaneously mitigating distortion generated by both the on-chip circuitry and mismatches due to time interleaving. In this paper, we describe the pNLEQ architecture and present measurements of its performance.
|Number of pages||12|
|Journal||IEEE Journal on Selected Topics in Signal Processing|
|State||Published - 2009|
Bibliographical noteFunding Information:
Manuscript received June 01, 2008; revised March 05, 2009. Current version published May 15, 2009. This work is sponsored by DARPA under Air Force Contract FA8721-05-C-0002. Opinions, interpretations, conclusions, and recommendations are those of the author and are not necessarily endorsed by the United States Government. The associate editor coordinating the review of this manuscript and approving it for publication was Prof. Naofal Al-Dhahir.
- Compressed sensing
- Mismatch distortions
- Multidimensional filter
- Nonlinear compensation
- Nonlinear equalization
- Polynomial filter
- Time-interleaved analog-to-digital converter (ADC)
ASJC Scopus subject areas
- Signal Processing
- Electrical and Electronic Engineering