Overlapping memory operations with circuit evaluation in reconfigurable computing

Yosi Ben-Asher, Daniel Citron, Gadi Haber

Research output: Contribution to journalArticlepeer-review


This paper considers the problem of compiling programs, written in a high-level programming language, into hardware circuits executed by an Field Programmable Gate Array (FPGA). In particular, we consider the problem of synthesising nested loops that frequently access array elements stored in an external memory (outside the FPGA). We propose an aggressive profile-based compilation scheme, based on loop unrolling and code flattening techniques, where array references from/to the external memory are overlapped with an uninterrupted hardware evaluation of the synthesised loop’s circuit. Experimental results show that large code segments can be compiled into circuits by using the proposed scheme.

Original languageEnglish
Pages (from-to)16-27
Number of pages12
JournalInternational Journal of Embedded Systems
Issue number1-2
StatePublished - 2006


  • Field Programmable Gate Array (FPGA)
  • compilation to hardware
  • highlevel synthesis

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture


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