Optimizing wait-states in the synthesis of memory references with unpredictable latencies

Keyphrases

• Latency 100%
• State Machine 100%
• Memory References 100%
• Wait States 100%
• Memory Latency 33%
• Active Memory 33%
• Compact State 33%
• Scheduler 16%
• One-state Reality 16%
• Caching 16%
• Simple Technique 16%
• Exponential number 16%
• Number of States 16%
• High-level Synthesis 16%
• Compiler 16%
• On chip 16%
• Memory Operations 16%
• Memory Module 16%
• Unknown Number 16%
• Multi-port Memory 16%
• DRAM Memory 16%
• Verilog 16%
• Linear States 16%
• Full State 16%
• Buffer Queue 16%

Computer Science

• State Machine 100%
• Memory Reference 100%
• Wait State 100%
• Clock Cycle 50%
• Memory Latency 33%
• Exponential Number 16%
• New-State 16%
• Verilog 16%
• Memory Operation 16%
• Multiport Memory 16%