Hardware Implementation of AES Using Area-Optimal Polynomials for Composite-Field Representation GF(2⁴)² of GF(2⁸)

Keyphrases

• Hardware Implementation 100%
• Composite Field 100%
• GF(28) 100%
• Field Representation 100%
• Small Area 33%
• Hardware Design 33%
• Affine 33%
• Input-output 33%
• Byte 33%
• Decryption 33%
• Encryption-decryption 33%
• Operating Mode 33%
• Area-based 33%
• Round Key 33%
• Optimal Representation 33%
• CMOS Implementation 33%
• 22nm CMOS 33%
• High Bandwidth 33%
• AES pipeline 33%
• AES Encryption 33%
• Field Extension 33%
• Extension of the Ground Field 33%

Computer Science

• Decryption 100%
• Hardware Implementation 100%
• Input/Output 50%
• Datapath 50%
• Hardware Design 50%
• Optimal Representation 50%
• Operating Mode 50%

Mathematics

• Polynomial 100%
• Advanced Encryption Standard 100%
• Decryption 28%
• Optimal Design 14%
• Round Key 14%