Hardware Implementation of AES Using Area-Optimal Polynomials for Composite-Field Representation GF(2⁴)² of GF(2⁸)

This paper discusses the question of optimizing AES hardware designs, by using the composite field representation GF(2⁴)² of the field GF(2⁸), that underlies the definition of AES. Here, GF(2⁴)² is the field extension of the ground field GF(2⁸) with an extension polynomial of the form x²+αx+β, where α and β are elements of field GF(2⁴). Previous designs with such representations used α = 1, which seemingly leads to some obvious savings. By contrast, we seek the optimal designs amongall the possibilities. Our designs are based on mapping the input, output, round keys, and the AES operations to and from any one of the 2880 possible representations of (2⁸) as (2⁴)². For each representation, we also explore three options for the affine/invaffine constants, resulting in a total of 8640 possible designs. We identify the smallest area representations for AES encryption-only, decryption-only, and for unified encryption-decryption. Surprisingly, the optimal representations in each case are different from each other. In addition, we identify six distinct representations that are optimal, based on operating-mode and AES pipeline depth. Among other results, we show here a set of high-bandwidth 16-byte AES datapaths with the extension polynomials of the form x²+αx+β where α ≠ 1, showing that the a-priori obvious choice of using α = 1, does not necessarily lead to the best result. We provide the full details of all the designs possibilities, together with their respective area, based on 22nm CMOS implementation.