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Generating ASIPs with Reduced Number of Connections to the Register-File
Yosi Ben Asher
, Irina Lipov
, Vladislav Tartakovsky
, Dror Tiv
Department of Computer Science
Research output
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Contribution to journal
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Article
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peer-review
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Keyphrases
Register File
100%
Number of Connections
100%
Application-specific Processors
100%
Instruction per Cycle
60%
Coprocessor
40%
Pipeline Specification
40%
Resource Utilization
20%
Small Sets
20%
Large Graphs
20%
Execution Units
20%
Pipeline Stages
20%
Machine Instruction
20%
Automatic Synthesis
20%
REG4
20%
Clock Frequency
20%
Reg1
20%
Reg3
20%
Convex Subgraph
20%
Verilog RTL
20%
Value Cycle
20%
Computer Science
Instructions per Cycle
100%
Coprocessor
66%
Execution Pipeline
66%
Verilog
33%
Pipeline Stage
33%
Clock Frequency
33%
Automatic Synthesis
33%
Branch Instruction
33%
Field Programmable Gate Arrays
33%