Generating ASIPs with reduced number of connections to the register-file

Keyphrases

• Register File 100%
• Number of Connections 100%
• Application-specific Processors 100%
• Instruction per Cycle 60%
• Coprocessor 40%
• Pipeline Specification 40%
• Resource Utilization 20%
• Small Sets 20%
• Large Graphs 20%
• Pipeline Stages 20%
• Machine Instruction 20%
• Automatic Synthesis 20%
• REG4 20%
• Clock Frequency 20%
• Reg3 20%
• Convex Subgraph 20%
• Verilog RTL 20%
• Value Cycle 20%

Computer Science

• Instructions per Cycle 100%
• Coprocessor 66%
• Verilog 33%
• Pipeline Stage 33%
• Clock Frequency 33%
• Automatic Synthesis 33%
• Execution Pipeline 33%
• Branch Instruction 33%
• Field Programmable Gate Arrays 33%