Finding the best compromise in compiling compound loops to Verilog

Keyphrases

• Conflicting Requirements 20%
• Execution Time 60%
• Expected number 20%
• Exploration Method 20%
• Hardware Configuration 100%
• Hardware Unit 20%
• Heat Levels 20%
• High-level Synthesis 20%
• Integer Linear Programming 20%
• Latency 20%
• Linear Programming Method 20%
• List Scheduling 20%
• Nested Loops 20%
• Number of Iterations 20%
• One-loop 20%
• Optimization Problem 20%
• Search Methods 20%
• Space Exploration 20%
• Subloop 80%
• Synthesis System 20%
• Time Use 20%
• Verilog 100%

Computer Science

• Computer Hardware 20%
• Execution Time 60%
• Experimental Result 20%
• Hardware Configuration 100%
• High Level Synthesis 20%
• Integer-Linear Programming 20%
• Nested Loop 20%
• Optimization Problem 20%
• Programming Technique 20%
• Search Procedure 20%
• Verilog 100%