Extending Booth algorithm to multiplications of three numbers on FPGAs

We propose an extension of Booth algorithm to perform multiplication of three numbers for faster FPGA implementation. This is based on the observation that when multiplying three numbers simultaneously the potential for arithmetic simplifications of intermediate terms increases. We use three types of simplifications of intermediate terms which are: Representing consecutive sequences of 1 as a subtraction two powers of 2; eliminating opposite-sign powers of 2 from intermediate terms and combining multiple occurrences of the same power to a single power of 2. Our experiments show a significant improvement in the expected number of elementary operations and in the synthesis times for Xilinx's Virtex-5.