Evaluation of circuits on the reconfigurable mesh

Yosi Ben Asher, Esti Stein

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The Reconfigurable Mesh (RM) is a grid of Processing Elements (PEs) that use dynamic reconfigurations to create varying bus-segments between its PEs. This allows the RM to perform computations such as sorting or counting in a constant number of steps. It has long been speculated that the RM's dynamic reconfiguration should replace the static reconfiguration architecture of the FPGA. In this work, we show that the RM can be used not only to accelerate specific computations such as sorting or summing but also for speeding up the main function of the FPGA, namely evaluation of Boolean Circuits (BCs). We propose an RM algorithm to evaluate BCs and show that it can be done without size blow-up. Moreover, like in the FPGA, it can be done using a grid of tri-state switching elements, rather than a grid of PEs as is the case with the regular RM. This model is called FPRM, and preliminary ASIC synthesis results illustrate that the FPRM architecture is about 2X faster and also more efficient in power/area than the FPGA routing infrastructure.

Original languageEnglish
Title of host publicationProceedings - 2019 IEEE 33rd International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages71-74
Number of pages4
ISBN (Electronic)9781728135106
DOIs
StatePublished - May 2019
Event33rd IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2019 - Rio de Janeiro, Brazil
Duration: 20 May 201924 May 2019

Publication series

NameProceedings - 2019 IEEE 33rd International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2019

Conference

Conference33rd IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2019
Country/TerritoryBrazil
CityRio de Janeiro
Period20/05/1924/05/19

Bibliographical note

Publisher Copyright:
© 2019 IEEE.

Keywords

  • Circuit evaluation
  • FPGA
  • Reconfigurable mesh

ASJC Scopus subject areas

  • Information Systems and Management
  • Artificial Intelligence
  • Computer Networks and Communications
  • Hardware and Architecture
  • Control and Optimization

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