## Abstract

We consider the problem of embedding a complete binary tree in square- or hexagonally-connected VLSI arrays of processing elements (PE's). This problem can be solved in a radically different manner from current layout techniques which are aimed at laying out a given graph in the plane. The difference is due to the fact that a PE can be used both as a tree node and as a connecting element between distant nodes. New embedding schemes are presented in which (asymptotically) 100 percent of the PE's are utilized as tree nodes. This is a significant savings over known schemes, which achieve 50 percent utilization (the well-known H-tree) and 71 percent for some hexagonal schemes. These schemes also speed up signal propagation from the root to the leaves.

Original language | English |
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Pages (from-to) | 1009-1018 |

Number of pages | 10 |

Journal | IEEE Transactions on Computers |

Volume | C-36 |

Issue number | 9 |

DOIs | |

State | Published - Sep 1987 |

Externally published | Yes |

## ASJC Scopus subject areas

- Software
- Theoretical Computer Science
- Hardware and Architecture
- Computational Theory and Mathematics