Abstract
Two models to realize boolean functions exist: Boolean circuits (BCs) a DAG of and/or/not-gates and Branching programs (BPs) a network of switching nodes wherein signals propagate through the switched nodes. Evaluation of BCs is inherently sequential (Based on the common belief that P neq NC) while BPs can be evaluated in parallel by verifying connectivity between the source and the sync nodes of an equivalent BP. This suggests a way to parallelize or evaluate in parallel inherently sequential computations (ISCs) by compiling them to BCs and then convert them to BPs. Our results suggest that BCs emanating from real computations can be converted to-BPs with no size blowup compare to the size of the original BC and in fact have a smaller size compared to the size of the original BCs.
| Original language | English |
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| Title of host publication | Proceedings - 2019 IEEE 33rd International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2019 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 655-662 |
| Number of pages | 8 |
| ISBN (Electronic) | 9781728135106 |
| DOIs | |
| State | Published - May 2019 |
| Event | 33rd IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2019 - Rio de Janeiro, Brazil Duration: 20 May 2019 → 24 May 2019 |
Publication series
| Name | Proceedings - 2019 IEEE 33rd International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2019 |
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Conference
| Conference | 33rd IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2019 |
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| Country/Territory | Brazil |
| City | Rio de Janeiro |
| Period | 20/05/19 → 24/05/19 |
Bibliographical note
Publisher Copyright:© 2019 IEEE.
Keywords
- Nondeterministic branching programs
- Parallel BFS
- Parallel evaluation
ASJC Scopus subject areas
- Information Systems and Management
- Artificial Intelligence
- Computer Networks and Communications
- Hardware and Architecture
- Control and Optimization