cpuC: A Dynamic Reconfigurable Architecture for CNNs Acceleration

The emergence use of convolutional neural networks in embedded systems calls for a power effcient light CPU architecture that can deliver an optimized degree of parallelism for trained CNNs (both memory and instructions per cycle). The proposed cpuC uses a crossbar to physicaly connect a set of units (Memory-ports, Registers, Muxes, Adders, Multipliers, etc.) in variouse topolgies forming diffrent sets of arithmetic circuits every clock-cycle. The resulting CPU is capable of computing the convolution of a complete k × k kernel in a single clock-cycle. Inspite of this massive parallelism the power consumption is very low (0.15 W) mainly due to the simplicity of the design. We compared a cpuC version designed to accelerate the convolutional layer of a given CNN to a GPU Geforce 840, executing an equivalent code. Synthesis results suggest that the cpuC accelerator can execute significantly more convolutions than the GPU assuming comparable die area.