Compiler-directed power management for superscalars

Jawad Haj-Yihia, Yosi Ben Asher, Efraim Rotem, Ahmad Yasin, Ran Ginosar

Research output: Contribution to journalArticlepeer-review


Modern superscalar CPUs contain large complex structures and diverse execution units, consuming wide dynamic power range. Building a power delivery network for the worst-case power consumption is not energy efficient and often is impossible to fit in small systems. Instantaneous power excursions can cause voltage droops. Power management algorithms are too slow to respond to instantaneous events. In this article, we propose a novel compiler-directed framework to address this problem. The framework is validated on a 4th Generation Intel® Core processor and with simulator on output trace. Up to 16% performance speedup is measured over baseline for the SPEC CPU2006 benchmarks.

Original languageEnglish
Article number48
JournalTransactions on Architecture and Code Optimization
Issue number4
StatePublished - 1 Dec 2014

Bibliographical note

Publisher Copyright:
© 2014 ACM.


  • Compiler assisted
  • Energy
  • Power management
  • Power modeling

ASJC Scopus subject areas

  • Software
  • Information Systems
  • Hardware and Architecture


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