Combining boolean gates and branching programs in one model can lead to faster circuits

The reconfigurable mesh (RM) is a powerful model for parallel computations. In spite of this power, the RM has not been realized mainly due to the assumption that the broadcastingcan be done in constant time regardless of the number of switches the broadcast has to pass through. Therefore, attempts were made to develop practical restricted models. We propose the Restricted-Reconfigurable Circuit (RRC) that allows broadcasting on the RMin the same time complexity as the theoretical model suggests. This model is a new approach which combines twobasic models of boolean functions f(x1,⋯, xn). These two basic models are the Boolean circuits (BCs) based on boolean gates triggering one another, and Branching Programs (BPs) where computation is done by reconfiguring switches and broadcasting signalsalong the resulting paths. The RRC is the model that combines the BCs and the BPs in one circuit. The delay of broadcasting over the RRC is computed as the maximum delay over all passes of switches in the model, and it is computed in units of n 1\k k >3 consecutive chain of BPsand log n sequence of boolean gates also counting as onetime unit of BCs. This delay is computed along the critical path of any BC, BP and RRC, thus allows us to compare pure BCs, pure BPs and RRCs. We believe it is also realistic giving slight advantage to BCs, as for practical values of n (n .