Bus-usage method for the analysis of reconfiguring networks algorithms

Yosi Ben-Asher, Assaf Schuster

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Reconfigurable networks attract increased attention recently, as an extremely strong parallel model which is realizable in hardware. In this work we consider the basic problem of gathering information which is dispersed among the nodes of the network. We analyze the complexity of the problem on reconfigurable linear-arrays. The analysis introduces a novel criteria for the efficiency of reconfigurable network algorithms, namely the Bus-Usage. The Bus-Usage quantity measures the utilization of the network sub-buses by the algorithm. It is shown how this yields bounds on the algorithm run-time, by deriving a run-time to bus-usage trade-off.

Original languageEnglish
Title of host publicationProceedings of the International Conference on Parallel Processing
PublisherPubl by IEEE
Pages146-149
Number of pages4
ISBN (Print)0818626720
StatePublished - 1992
EventProceedings of the 6th International Parallel Processing Symposium - Beverly Hills, CA, USA
Duration: 23 Mar 199226 Mar 1992

Publication series

NameProceedings of the International Conference on Parallel Processing
ISSN (Print)0190-3918

Conference

ConferenceProceedings of the 6th International Parallel Processing Symposium
CityBeverly Hills, CA, USA
Period23/03/9226/03/92

ASJC Scopus subject areas

  • Hardware and Architecture

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