@inproceedings{3b5b55f1614247b89142240b00445199,
title = "Automatic memory partitioning: Increasing memory parallelism via data structure partitioning",
abstract = "In high-level synthesis, pipelined designs are often restricted by the number of memory banks available to the synthesis system. Using multiple memory banks can improve the performance of accelerated applications. Currently, programmers must manually assign data structures to specific memory banks on the accelerator. This paper presents Automatic Memory Partitioning, a method for automatically partitioning data structures into multiple memory banks for increased parallelism and performance. We use source code instrumentation to collect memory traces in order to detect linear memory access patterns. The memory traces are used to split data structures into disjoint memory regions and determine which segments may benefit from parallel memory access. Experiments show significant improvements in performance while using a minimal number of memory banks.",
keywords = "FPGA, Memory, Parallelism",
author = "Asher, {Yosi Ben} and Nadav Rotem",
year = "2010",
doi = "10.1145/1878961.1878989",
language = "English",
isbn = "9781605589053",
series = "Embedded Systems Week 2010 - Proceedings of the 8th IEEE/ACM/IFIP International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CODES+ISSS'2010",
pages = "155--161",
booktitle = "Embedded Systems Week 2010 - Proceedings of the 8th IEEE/ACM/IFIP International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CODES+ISSS'10",
note = "6th Embedded Systems Week, ESWEEK 2010 - 8th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS'10 ; Conference date: 24-10-2010 Through 29-10-2010",
}