An FPGA scalable parallel viterbi decoder

Computer Science

• Parallelism 100%
• Received Symbol 100%
• Linear Speedup 100%
• Field Programmable Gate Arrays 100%
• Matrix Multiplication 50%
• Verilog 50%
• Parallel Implementation 50%
• Sequential Process 50%
• Sequential Decoder 50%
• Minimal Amount 50%
• Decoding Process 50%
• Parallel Version 50%
• Embedded System 50%

Keyphrases

• Trellis 100%
• Viterbi Decoder 100%
• Parallelizing 60%
• Parallelization 40%
• Linear Speedup 40%
• Minimal Path 40%
• Decoder 20%
• Sequential Process 20%
• Matrix multiplication 20%
• Decoding Process 20%
• Embedded Systems 20%
• Parallel Version 20%
• Verilog 20%
• Parallel Implementation 20%
• Matrix Sequence 20%
• Sequential Decoder 20%
• Parallel Decoder 20%
• Data Symbol 20%
• Noisy Channel 20%