An FPGA scalable parallel viterbi decoder

Viterbi decoders are an essential component in many embedded systems used for decoding streams of N data symbols over noisy channels. The decoding process is a sequential process wherein the decoder builds a trellis for N received symbols and then it traverses the trellis back computing the path in the trellis that implies the minimal amount of corrections in the bits of the N received symbols. Several techniques have been developed to increase the amount of parallelism of Viterbi decoders, showing building the trellis can be parallelized however to the selecting the minimal path proved harder to parallelize. In this work, we show that both building the Trellis and computing the minimal path can be parallelized as a sequence of matrix multiplications. This yields a parallel implementation with a linear speedup of order N/P+P where P is any amount of the desired parallelism in the circuit. We implemented a Verilog-generator that for any set of parameters generates an optimized sequential decoder and an optimized parallel decoder. We thus able to verify that the parallel version can obtain linear speedups.