## Abstract

This paper presents a three-integers multiplication algorithm R = A∗X∗Y for Reconfigurable Mesh (RM). It is based on a three-integer multiplication algorithm for faster FPGA implementations. We show that multiplying three integers of n bits can be performed on a 3D RM of size (3n + logn + 1) × (2√n+1 +3) × √n+1 using 44 + 18 · log log MNO steps, where MNO is a bound which is related to the number of sequences of '1's in the multiplied numbers. The value of MNO is bounded by n but experimentally we show that on the average it is √n. Two algorithms for solving multiplication on a RM exists and their techniques are asymptotically better time wise, O(1) and O(log∗n), but they suffer from large hidden constants and slow data insertion time (O(√n)) respectively. The proposed algorithm is relatively simple and faster on the average (via sampling input values) then the previous two algorithms thus contributes in making the RM a practical and feasible model. Our experiments show a significant improvement in the expected number of elementary operations for the proposed algorithm.

Original language | English |
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Article number | 1550009 |

Journal | Journal of Interconnection Networks |

Volume | 16 |

Issue number | 1 |

DOIs | |

State | Published - 1 Mar 2016 |

### Bibliographical note

Funding Information:This project was supported in part (or in whole) by a grant from the Minnesota Department of Commerce, Division of Energy Resources, through the Conservation Applied Research and Development (CARD) program, which is funded by Minnesota ratepayers.

Publisher Copyright:

© 2016 World Scientific Publishing Company.

## Keywords

- Reconfigurable mesh
- booth multiplication
- cartesian addition
- extended summing

## ASJC Scopus subject areas

- Computer Networks and Communications