A study of manycore shared memory architecture as a way to build SOC applications

Keyphrases

• Communication Networks 100%
• Memory Module 100%
• Shared Memory 100%
• Many-core 100%
• Shared Memory Architecture 100%
• Small Core 33%
• Hardware Accelerator 33%
• Hash Function 33%
• Hashing 33%
• Parallel Algorithm 33%
• Execution Time 33%
• Caching 33%
• Number of Cores 33%
• 32-bit 33%
• Load Balancing 33%
• Highly Parallel 33%
• Theoretical Scheme 33%
• Parallel Programming 33%
• FPGA Routing 33%
• Routing Mechanism 33%
• Cache Consistency 33%
• Memory Address Space 33%
• Shared Address Space 33%
• Theoretical Construction 33%
• Routing Grid 33%
• Main Memory 33%
• Rehashing 33%
• Virtex-7 33%
• Universal Hash Function 33%

Computer Science

• Communication Network 100%
• Shared Memories 100%
• Shared Memory Architecture 100%
• Speed-up 33%
• Hash Function 33%
• Parallel Algorithms 33%
• Load Balancing 33%
• Execution Time 33%
• Hashing 33%
• Growing Complexity 33%
• Parallel Program 33%
• Application Specific Integrated Circuit 33%
• Cache Consistency 33%
• Memory Address 33%
• Main Memory 33%
• Hardware Accelerator 33%
• Universal Hash Function 33%