A methodology for OLTP micro-Architectural analysis

Utku Sirin; Ahmad Yasin; Anastasia Ailamaki

doi:10.1145/3076113.3076116

A methodology for OLTP micro-Architectural analysis

Utku Sirin, Ahmad Yasin, Anastasia Ailamaki

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Micro-Architectural analysis is critical to investigate the interaction between workloads and processors. While today's aggressive out-of-order processors provide a rich set of performance events for deep execution cycle analysis, OLTP characterization studies usually use a cache-miss-based method (CMBM). In this work, we investigate the validity and the functionality of CMBM by comparing it with Intel's state-of-The-Art Top-down Micro-Architecture Analysis Method (TMAM) for OLTP workloads. We show that, while CMBM and TMAM provide a similar high-level micro-Architectural behavior, it is inadequate for a fine-grained micro-Architectural analysis. We further show that TMAM underestimates memory stalls. We optimize TMAM's execution cycle breakdown, and improve its estimation of memory stalls up to 50%.

Original language	English
Title of host publication	Proceedings of the 13th International Workshop on Data Management on New Hardware, DAMON 2017
Publisher	Association for Computing Machinery, Inc
ISBN (Electronic)	9781450350259
DOIs	https://doi.org/10.1145/3076113.3076116
State	Published - 14 May 2017
Externally published	Yes
Event	13th International Workshop on Data Management on New Hardware, DAMON 2017 - Chicago, United States Duration: 14 May 2017 → 19 May 2017

Publication series

Name	Proceedings of the 13th International Workshop on Data Management on New Hardware, DAMON 2017

Conference

Conference	13th International Workshop on Data Management on New Hardware, DAMON 2017
Country/Territory	United States
City	Chicago
Period	14/05/17 → 19/05/17

Bibliographical note

Publisher Copyright:
©2017 ACM.

ASJC Scopus subject areas

Hardware and Architecture

Access to Document

10.1145/3076113.3076116

Cite this

Sirin, U., Yasin, A., & Ailamaki, A. (2017). A methodology for OLTP micro-Architectural analysis. In Proceedings of the 13th International Workshop on Data Management on New Hardware, DAMON 2017 Article 3076116 (Proceedings of the 13th International Workshop on Data Management on New Hardware, DAMON 2017). Association for Computing Machinery, Inc. https://doi.org/10.1145/3076113.3076116

@inproceedings{95dc57a73bd545d697418b54b2b35761,

title = "A methodology for OLTP micro-Architectural analysis",

abstract = "Micro-Architectural analysis is critical to investigate the interaction between workloads and processors. While today's aggressive out-of-order processors provide a rich set of performance events for deep execution cycle analysis, OLTP characterization studies usually use a cache-miss-based method (CMBM). In this work, we investigate the validity and the functionality of CMBM by comparing it with Intel's state-of-The-Art Top-down Micro-Architecture Analysis Method (TMAM) for OLTP workloads. We show that, while CMBM and TMAM provide a similar high-level micro-Architectural behavior, it is inadequate for a fine-grained micro-Architectural analysis. We further show that TMAM underestimates memory stalls. We optimize TMAM's execution cycle breakdown, and improve its estimation of memory stalls up to 50%.",

author = "Utku Sirin and Ahmad Yasin and Anastasia Ailamaki",

note = "Publisher Copyright: {\textcopyright}2017 ACM.; 13th International Workshop on Data Management on New Hardware, DAMON 2017 ; Conference date: 14-05-2017 Through 19-05-2017",

year = "2017",

month = may,

day = "14",

doi = "10.1145/3076113.3076116",

language = "English",

series = "Proceedings of the 13th International Workshop on Data Management on New Hardware, DAMON 2017",

publisher = "Association for Computing Machinery, Inc",

booktitle = "Proceedings of the 13th International Workshop on Data Management on New Hardware, DAMON 2017",

}

Sirin, U, Yasin, A & Ailamaki, A 2017, A methodology for OLTP micro-Architectural analysis. in Proceedings of the 13th International Workshop on Data Management on New Hardware, DAMON 2017., 3076116, Proceedings of the 13th International Workshop on Data Management on New Hardware, DAMON 2017, Association for Computing Machinery, Inc, 13th International Workshop on Data Management on New Hardware, DAMON 2017, Chicago, United States, 14/05/17. https://doi.org/10.1145/3076113.3076116

A methodology for OLTP micro-Architectural analysis. / Sirin, Utku; Yasin, Ahmad; Ailamaki, Anastasia.
Proceedings of the 13th International Workshop on Data Management on New Hardware, DAMON 2017. Association for Computing Machinery, Inc, 2017. 3076116 (Proceedings of the 13th International Workshop on Data Management on New Hardware, DAMON 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A methodology for OLTP micro-Architectural analysis

AU - Sirin, Utku

AU - Yasin, Ahmad

AU - Ailamaki, Anastasia

PY - 2017/5/14

Y1 - 2017/5/14

N2 - Micro-Architectural analysis is critical to investigate the interaction between workloads and processors. While today's aggressive out-of-order processors provide a rich set of performance events for deep execution cycle analysis, OLTP characterization studies usually use a cache-miss-based method (CMBM). In this work, we investigate the validity and the functionality of CMBM by comparing it with Intel's state-of-The-Art Top-down Micro-Architecture Analysis Method (TMAM) for OLTP workloads. We show that, while CMBM and TMAM provide a similar high-level micro-Architectural behavior, it is inadequate for a fine-grained micro-Architectural analysis. We further show that TMAM underestimates memory stalls. We optimize TMAM's execution cycle breakdown, and improve its estimation of memory stalls up to 50%.

AB - Micro-Architectural analysis is critical to investigate the interaction between workloads and processors. While today's aggressive out-of-order processors provide a rich set of performance events for deep execution cycle analysis, OLTP characterization studies usually use a cache-miss-based method (CMBM). In this work, we investigate the validity and the functionality of CMBM by comparing it with Intel's state-of-The-Art Top-down Micro-Architecture Analysis Method (TMAM) for OLTP workloads. We show that, while CMBM and TMAM provide a similar high-level micro-Architectural behavior, it is inadequate for a fine-grained micro-Architectural analysis. We further show that TMAM underestimates memory stalls. We optimize TMAM's execution cycle breakdown, and improve its estimation of memory stalls up to 50%.

UR - http://www.scopus.com/inward/record.url?scp=85021727112&partnerID=8YFLogxK

U2 - 10.1145/3076113.3076116

DO - 10.1145/3076113.3076116

M3 - Conference contribution

AN - SCOPUS:85021727112

T3 - Proceedings of the 13th International Workshop on Data Management on New Hardware, DAMON 2017

BT - Proceedings of the 13th International Workshop on Data Management on New Hardware, DAMON 2017

PB - Association for Computing Machinery, Inc

T2 - 13th International Workshop on Data Management on New Hardware, DAMON 2017

Y2 - 14 May 2017 through 19 May 2017

ER -

A methodology for OLTP micro-Architectural analysis

Abstract

Publication series

Conference

Bibliographical note

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this