A 2.1GHz 6.5mW 64-bit unified PopCount/BitScan datapath unit for 65nm high-performance microprocessor execution cores

Rajaraman Ramanarayanan; Sanu Mathew; Vasantha Erraguntla; Ram Krishnamurthy; Shay Gueron

doi:10.1109/VLSI.2008.75

A 2.1GHz 6.5mW 64-bit unified PopCount/BitScan datapath unit for 65nm high-performance microprocessor execution cores

Rajaraman Ramanarayanan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy, Shay Gueron

Department of Mathematics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper describes a unified PopCount/ BitScanForward/BitScanReverse datapath circuit designed for 2.1GHz operation with total power consumption of 6.5mW, targeted for 65nm 64-bit microprocessor execution cores. The unified datapath uses a hybrid 3:2 compressor-based Wallace tree to count the number of '1's in the 64-bit input, along with a novel encoding scheme that enables reuse of the same tree to identify the bit-location of the 1^st set bit when scanning the input in the forward and reverse directions. This circuit thus combines the functions of 3 separate units, enabling 26% reduction in total energy and 20% lower area, while achieving single-cycle latency & throughput.

Original language	English
Title of host publication	Proceedings - 21st International Conference on VLSI Design, VLSI DESIGN 2008
Pages	273-278
Number of pages	6
DOIs	https://doi.org/10.1109/VLSI.2008.75
State	Published - 2008
Event	21st International Conference on VLSI Design, VLSI DESIGN 2008 - Hyderabad, India Duration: 4 Jan 2008 → 8 Jan 2008

Publication series

Name	Proceedings of the IEEE International Frequency Control Symposium and Exposition

Conference

Conference	21st International Conference on VLSI Design, VLSI DESIGN 2008
Country/Territory	India
City	Hyderabad
Period	4/01/08 → 8/01/08

ASJC Scopus subject areas

General Engineering

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10.1109/VLSI.2008.75

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Ramanarayanan, R., Mathew, S., Erraguntla, V., Krishnamurthy, R., & Gueron, S. (2008). A 2.1GHz 6.5mW 64-bit unified PopCount/BitScan datapath unit for 65nm high-performance microprocessor execution cores. In Proceedings - 21st International Conference on VLSI Design, VLSI DESIGN 2008 (pp. 273-278). Article 4450514 (Proceedings of the IEEE International Frequency Control Symposium and Exposition). https://doi.org/10.1109/VLSI.2008.75

Ramanarayanan, Rajaraman ; Mathew, Sanu ; Erraguntla, Vasantha et al. / A 2.1GHz 6.5mW 64-bit unified PopCount/BitScan datapath unit for 65nm high-performance microprocessor execution cores. Proceedings - 21st International Conference on VLSI Design, VLSI DESIGN 2008. 2008. pp. 273-278 (Proceedings of the IEEE International Frequency Control Symposium and Exposition).

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title = "A 2.1GHz 6.5mW 64-bit unified PopCount/BitScan datapath unit for 65nm high-performance microprocessor execution cores",

abstract = "This paper describes a unified PopCount/ BitScanForward/BitScanReverse datapath circuit designed for 2.1GHz operation with total power consumption of 6.5mW, targeted for 65nm 64-bit microprocessor execution cores. The unified datapath uses a hybrid 3:2 compressor-based Wallace tree to count the number of '1's in the 64-bit input, along with a novel encoding scheme that enables reuse of the same tree to identify the bit-location of the 1st set bit when scanning the input in the forward and reverse directions. This circuit thus combines the functions of 3 separate units, enabling 26% reduction in total energy and 20% lower area, while achieving single-cycle latency & throughput.",

author = "Rajaraman Ramanarayanan and Sanu Mathew and Vasantha Erraguntla and Ram Krishnamurthy and Shay Gueron",

year = "2008",

doi = "10.1109/VLSI.2008.75",

language = "English",

isbn = "0769530834",

series = "Proceedings of the IEEE International Frequency Control Symposium and Exposition",

pages = "273--278",

booktitle = "Proceedings - 21st International Conference on VLSI Design, VLSI DESIGN 2008",

note = "21st International Conference on VLSI Design, VLSI DESIGN 2008 ; Conference date: 04-01-2008 Through 08-01-2008",

}

Ramanarayanan, R, Mathew, S, Erraguntla, V, Krishnamurthy, R & Gueron, S 2008, A 2.1GHz 6.5mW 64-bit unified PopCount/BitScan datapath unit for 65nm high-performance microprocessor execution cores. in Proceedings - 21st International Conference on VLSI Design, VLSI DESIGN 2008., 4450514, Proceedings of the IEEE International Frequency Control Symposium and Exposition, pp. 273-278, 21st International Conference on VLSI Design, VLSI DESIGN 2008, Hyderabad, India, 4/01/08. https://doi.org/10.1109/VLSI.2008.75

A 2.1GHz 6.5mW 64-bit unified PopCount/BitScan datapath unit for 65nm high-performance microprocessor execution cores. / Ramanarayanan, Rajaraman; Mathew, Sanu; Erraguntla, Vasantha et al.
Proceedings - 21st International Conference on VLSI Design, VLSI DESIGN 2008. 2008. p. 273-278 4450514 (Proceedings of the IEEE International Frequency Control Symposium and Exposition).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - This paper describes a unified PopCount/ BitScanForward/BitScanReverse datapath circuit designed for 2.1GHz operation with total power consumption of 6.5mW, targeted for 65nm 64-bit microprocessor execution cores. The unified datapath uses a hybrid 3:2 compressor-based Wallace tree to count the number of '1's in the 64-bit input, along with a novel encoding scheme that enables reuse of the same tree to identify the bit-location of the 1st set bit when scanning the input in the forward and reverse directions. This circuit thus combines the functions of 3 separate units, enabling 26% reduction in total energy and 20% lower area, while achieving single-cycle latency & throughput.

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Ramanarayanan R, Mathew S, Erraguntla V, Krishnamurthy R, Gueron S. A 2.1GHz 6.5mW 64-bit unified PopCount/BitScan datapath unit for 65nm high-performance microprocessor execution cores. In Proceedings - 21st International Conference on VLSI Design, VLSI DESIGN 2008. 2008. p. 273-278. 4450514. (Proceedings of the IEEE International Frequency Control Symposium and Exposition). doi: 10.1109/VLSI.2008.75

A 2.1GHz 6.5mW 64-bit unified PopCount/BitScan datapath unit for 65nm high-performance microprocessor execution cores

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