53Gbps native GF(24)2 composite-field AES-encrypt/decrypt accelerator for content-protection in 45nm high-performance microprocessors

Sanu K. Mathew; Farhana Sheikh; Arnav Agarwal; Michael Kounavis; Steven K. Hsu; Himanshu Kaul; Mark A. Anders; Ram K. Krishnamurthy; Shay Gueron

doi:10.1109/VLSIC.2010.5560310

53Gbps native GF(24)2 composite-field AES-encrypt/decrypt accelerator for content-protection in 45nm high-performance microprocessors

Sanu K. Mathew
, Farhana Sheikh
, Arnav Agarwal
, Michael Kounavis
, Steven K. Hsu
, Himanshu Kaul
, Mark A. Anders
, Ram K. Krishnamurthy
, Shay Gueron

Department of Mathematics

Research output: Chapter in Book/Report/Conference proceeding › Chapter › peer-review

Abstract

An on-die, reconfigurable AES encrypt/decrypt hardware accelerator is fabricated in 45nm CMOS, targeted for content-protection in high-performance microprocessors. Compared to conventional AES implementations, this design computes the entire AES round in native GF(24)2 composite-field with one-time GF(28)-to-GF(24)2 mapping cost amortized over multiple AES iterations. This approach along with a fused Mix/InvMixColumns circuit and folded ShiftRow datapath results in 20% area savings and 67% reduction in worst-case interconnect length, enabling AES-128/192/256 ECB block throughput of 53/44/38Gbps, 125mW power measured at 1.1V, 50°C.

Original language	English
Title of host publication	2010 Symposium on VLSI Circuits
Pages	169-170
Number of pages	2
DOIs	https://doi.org/10.1109/VLSIC.2010.5560310
State	Published - 2010
Event	2010 24th Symposium on VLSI Circuits, VLSIC 2010 - Honolulu, HI, United States Duration: 16 Jun 2010 → 18 Jun 2010

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference	2010 24th Symposium on VLSI Circuits, VLSIC 2010
Country/Territory	United States
City	Honolulu, HI
Period	16/06/10 → 18/06/10

Keywords

Microprocessors
Polynomials
Throughput
Hardware
Encryption
Integrated circuit interconnections

Access to Document

10.1109/VLSIC.2010.5560310

Cite this

Mathew, S. K., Sheikh, F., Agarwal, A., Kounavis, M., Hsu, S. K., Kaul, H., Anders, M. A., Krishnamurthy, R. K., & Gueron, S. (2010). 53Gbps native GF(24)2 composite-field AES-encrypt/decrypt accelerator for content-protection in 45nm high-performance microprocessors. In 2010 Symposium on VLSI Circuits (pp. 169-170). Article 5560310 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.1109/VLSIC.2010.5560310

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title = "53Gbps native GF(24)2 composite-field AES-encrypt/decrypt accelerator for content-protection in 45nm high-performance microprocessors",

abstract = "An on-die, reconfigurable AES encrypt/decrypt hardware accelerator is fabricated in 45nm CMOS, targeted for content-protection in high-performance microprocessors. Compared to conventional AES implementations, this design computes the entire AES round in native GF(24)2 composite-field with one-time GF(28)-to-GF(24)2 mapping cost amortized over multiple AES iterations. This approach along with a fused Mix/InvMixColumns circuit and folded ShiftRow datapath results in 20\% area savings and 67\% reduction in worst-case interconnect length, enabling AES-128/192/256 ECB block throughput of 53/44/38Gbps, 125mW power measured at 1.1V, 50°C.",

keywords = "Microprocessors, Polynomials, Throughput, Hardware, Encryption, Integrated circuit interconnections",

author = "Mathew, \{Sanu K.\} and Farhana Sheikh and Arnav Agarwal and Michael Kounavis and Hsu, \{Steven K.\} and Himanshu Kaul and Anders, \{Mark A.\} and Krishnamurthy, \{Ram K.\} and Shay Gueron",

year = "2010",

doi = "10.1109/VLSIC.2010.5560310",

language = "English",

isbn = "9781424476367",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

pages = "169--170",

booktitle = "2010 Symposium on VLSI Circuits",

note = "2010 24th Symposium on VLSI Circuits, VLSIC 2010 ; Conference date: 16-06-2010 Through 18-06-2010",

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Mathew, SK, Sheikh, F, Agarwal, A, Kounavis, M, Hsu, SK, Kaul, H, Anders, MA, Krishnamurthy, RK & Gueron, S 2010, 53Gbps native GF(24)2 composite-field AES-encrypt/decrypt accelerator for content-protection in 45nm high-performance microprocessors. in 2010 Symposium on VLSI Circuits., 5560310, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 169-170, 2010 24th Symposium on VLSI Circuits, VLSIC 2010, Honolulu, HI, United States, 16/06/10. https://doi.org/10.1109/VLSIC.2010.5560310

53Gbps native GF(24)2 composite-field AES-encrypt/decrypt accelerator for content-protection in 45nm high-performance microprocessors. / Mathew, Sanu K.; Sheikh, Farhana; Agarwal, Arnav et al.
2010 Symposium on VLSI Circuits. 2010. p. 169-170 5560310 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Chapter › peer-review

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AU - Mathew, Sanu K.

AU - Sheikh, Farhana

AU - Agarwal, Arnav

AU - Kounavis, Michael

AU - Hsu, Steven K.

AU - Kaul, Himanshu

AU - Anders, Mark A.

AU - Krishnamurthy, Ram K.

AU - Gueron, Shay

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AB - An on-die, reconfigurable AES encrypt/decrypt hardware accelerator is fabricated in 45nm CMOS, targeted for content-protection in high-performance microprocessors. Compared to conventional AES implementations, this design computes the entire AES round in native GF(24)2 composite-field with one-time GF(28)-to-GF(24)2 mapping cost amortized over multiple AES iterations. This approach along with a fused Mix/InvMixColumns circuit and folded ShiftRow datapath results in 20% area savings and 67% reduction in worst-case interconnect length, enabling AES-128/192/256 ECB block throughput of 53/44/38Gbps, 125mW power measured at 1.1V, 50°C.

KW - Microprocessors

KW - Polynomials

KW - Throughput

KW - Hardware

KW - Encryption

KW - Integrated circuit interconnections

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ER -

53Gbps native GF(24)2 composite-field AES-encrypt/decrypt accelerator for content-protection in 45nm high-performance microprocessors

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Keywords

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