53Gbps native GF(24)2 composite-field AES-encrypt/decrypt accelerator for content-protection in 45nm high-performance microprocessors

Sanu K. Mathew, Farhana Sheikh, Arnav Agarwal, Michael Kounavis, Steven K. Hsu, Himanshu Kaul, Mark A. Anders, Ram K. Krishnamurthy, Shay Gueron

Research output: Chapter in Book/Report/Conference proceedingChapterpeer-review

Abstract

An on-die, reconfigurable AES encrypt/decrypt hardware accelerator is fabricated in 45nm CMOS, targeted for content-protection in high-performance microprocessors. Compared to conventional AES implementations, this design computes the entire AES round in native GF(24)2 composite-field with one-time GF(28)-to-GF(24)2 mapping cost amortized over multiple AES iterations. This approach along with a fused Mix/InvMixColumns circuit and folded ShiftRow datapath results in 20% area savings and 67% reduction in worst-case interconnect length, enabling AES-128/192/256 ECB block throughput of 53/44/38Gbps, 125mW power measured at 1.1V, 50°C.
Original languageEnglish
Title of host publication2010 Symposium on VLSI Circuits
Pages169-170
Number of pages2
DOIs
StatePublished - 2010
Event2010 24th Symposium on VLSI Circuits, VLSIC 2010 - Honolulu, HI, United States
Duration: 16 Jun 201018 Jun 2010

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference2010 24th Symposium on VLSI Circuits, VLSIC 2010
Country/TerritoryUnited States
CityHonolulu, HI
Period16/06/1018/06/10

Keywords

  • Microprocessors
  • Polynomials
  • Throughput
  • Hardware
  • Encryption
  • Integrated circuit interconnections

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