@inbook{13656817e1f545c89387c8060e072c04,
title = "53Gbps native GF(24)2 composite-field AES-encrypt/decrypt accelerator for content-protection in 45nm high-performance microprocessors",
abstract = "An on-die, reconfigurable AES encrypt/decrypt hardware accelerator is fabricated in 45nm CMOS, targeted for content-protection in high-performance microprocessors. Compared to conventional AES implementations, this design computes the entire AES round in native GF(24)2 composite-field with one-time GF(28)-to-GF(24)2 mapping cost amortized over multiple AES iterations. This approach along with a fused Mix/InvMixColumns circuit and folded ShiftRow datapath results in 20% area savings and 67% reduction in worst-case interconnect length, enabling AES-128/192/256 ECB block throughput of 53/44/38Gbps, 125mW power measured at 1.1V, 50°C.",
keywords = "Microprocessors, Polynomials, Throughput, Hardware, Encryption, Integrated circuit interconnections",
author = "Mathew, {Sanu K.} and Farhana Sheikh and Arnav Agarwal and Michael Kounavis and Hsu, {Steven K.} and Himanshu Kaul and Anders, {Mark A.} and Krishnamurthy, {Ram K.} and Shay Gueron",
year = "2010",
doi = "10.1109/VLSIC.2010.5560310",
language = "English",
isbn = "9781424476367",
series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",
pages = "169--170",
booktitle = "2010 Symposium on VLSI Circuits",
note = "2010 24th Symposium on VLSI Circuits, VLSIC 2010 ; Conference date: 16-06-2010 Through 18-06-2010",
}