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Keyphrases
Latency
100%
Multiple Clocks
75%
Execution Time
75%
High-level Synthesis
75%
RISC-V
75%
VLIW Architecture
75%
Pipelined Architecture
75%
CPU Architecture
75%
CNN Acceleration
75%
Dynamic Reconfigurable Architecture
75%
GPU
75%
Throughput Efficiency
50%
Power Efficiency
50%
Computational Throughput
50%
Computational Power
50%
Straight Line
37%
Line Codes
37%
Longest Path
37%
Common Divisor
37%
Die Area
37%
Convolutional Layer
37%
Crossbar
37%
Degree of Parallelism
37%
Muxes
37%
K-kernel
37%
Single Clock
37%
Effcient
37%
Code Equivalence
37%
Parallel Arrangement
24%
Pipeline Scheduling
24%
Pipeline Arrangement
24%
Power Utilization
24%
FPGA Realization
24%
Embedded Systems
24%
Resource Utilization
24%
Schematic Model
24%
Pipeline Stages
24%
Instruction-level Parallelism
24%
Computer Science
Clock Cycle
75%
Execution Time
75%
Pipeline Architecture
75%
reconfigurable architecture
75%
High Level Synthesis
56%
Power Efficiency
50%
Functional Unit
50%
Field Programmable Gate Arrays
50%
Longest Path
37%
Convolution
37%
Multiple Functional Unit
24%
Schematic Diagram
24%
Pipeline Stage
24%
Embedded System
24%
Resource Utilisation
24%
Circuit Diagrams
24%
Instruction-Level Parallelism
24%
Research Effort
24%